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integrated circuit systems, inc. ics954201 0819h?02/17/06 pin configuration recommended application: ck410m clock, intel yellow cover part output features: 2 - 0.7v current-mode differential cpu pairs 7 - 0.7v current-mode differential src pair for sata and pci-e 1 - 0.7v current-mode differential cpu/src selectable pair 4 - pci (33mhz) 2 - pciclk_f, (33mhz) free-running 1 - usb, 48mhz 1 - dot, 96mhz, 0.7v current differential pair 1 - ref, 14.318mhz key specifications: cpu outputs cycle-cycle jitter < 85ps src outputs cycle-cycle jitter < 125ps pci outputs cycle-cycle jitter < 500ps +/- 300ppm frequency accuracy on cpu & src clocks +/- 100ppm frequency accuracy on usb clocks programmable timing control hub? for mobile p 4 ? systems functionality features/benefits: supports tight ppm accuracy clocks for serial-ata and pci-express supports spread spectrum modulation, 0 to -0.5% down spread supports cpu clocks up to 400mhz uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning supports undriven differential cpu, src pair in pd# for power management. 56-pin ssop & tssop vddpci 1 56 pciclk2 gnd 2 55 pci/src_stop# pciclk3 3 54 cpu_stop# pciclk4 4 53 fs_c/test_sel pciclk5 5 52 refout gnd 6 51 gnd vddpci 7 50 x1 itp_en/pciclk_f0 8 49 x2 pciclk_f1 9 48 vddref vtt_pwrgd#/pd 10 47 sdata vdd4811 46sclk usb_48mhz/fs_a 12 45 gnd gnd 13 44 cpuclkt0 dott_96mhz 14 43 cpuclkc0 dotc_96mhz 15 42 vddcpu fs_b/test_mode 16 41 cpuclkt1 srcclkt0 17 40 cpuclkc1 srcclkc0 18 39 iref srcclkt1 19 38 gnda srcclkc1 20 37 vdda vddsrc 21 36 cpuclkt2_itp/srcclkt7 srcclkt2 22 35 cpuclkc2_itp/srcclkc7 srcclkc2 23 34 vddsrc srcclkt3 24 33 srcclkt6 srcclkc3 25 32 srcclkc6 srcclkt4_sata 26 31 srcclkt5 srcclkc4_sata 27 30 srcclkc5 vddsrc 28 29 gnd ics954201 fs_c 1 fs_b 2 fs_a 2 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 1 1 1 14.318 48.00 96.00 1. fs_c is a three-level input. please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs_b and fs_a are low-threshold inputs. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. reserved
2 integrated circuit systems, inc. ics954201 0819h?02/17/06 pin description pin # pin name pin type description 1 vddpci pwr power supply for pci clo cks, nominal 3.3v 2 gnd pwr ground pin. 3 pciclk3 out pci clock output. 4 pciclk4 out pci clock output. 5 pciclk5 out pci clock output. 6 gnd pwr ground pin. 7 vddpci pwr power supply for pci clo cks, nominal 3.3v 8 itp_en/pciclk_f0 i/o free running pci clock not affected by pci_stop#. itp_en: latched input to select pin functionality 1 = cpu_itp pair 0 = src pair 9 pciclk_f1 out free running pci clock not affected by pci_stop# . 10 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks, plls and the crystal oscillator are stopped. 11 vdd48 pwr power pin for the 48mhz output.3.3v 12 usb_48mhz/fs_a i/o frequency select latch input pin / fixed 48mhz usb clock output. 3.3v. 13 gnd pwr ground pin. 14 dott_96mhz out true clock of differential pair for 96.00mhz dot clock. 15 dotc_96mhz out complement clock of differential pair for 96.00mhz dot clock. 16 fs_b/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 17 srcclkt0 out true clock of differential src clock pair. 18 srcclkc0 out complement clock of differential src clock pair. 19 srcclkt1 out true clock of differential src clock pair. 20 srcclkc1 out complement clock of differential src clock pair. 21 vddsrc pwr supply for src clo cks, 3.3v nominal 22 srcclkt2 out true clock of differential src clock pair. 23 srcclkc2 out complement clock of differential src clock pair. 24 srcclkt3 out true clock of differential src clock pair. 25 srcclkc3 out complement clock of differential src clock pair. 26 srcclkt4_sata out true clock of differential src/sata pair. 27 srcclkc4_sata out complement clock of differential src/sata pair. 28 vddsrc pwr supply for src clo cks, 3.3v nominal
3 integrated circuit systems, inc. ics954201 0819h?02/17/06 pin description (continued) pin # pin name type description 29 gnd pwr ground pin. 30 srcclkc5 out complement clock of differential src clock pair. 31 srcclkt5 out true clock of differential src clock pair. 32 srcclkc6 out complement clock of differential src clock pair. 33 srcclkt6 out true clock of differential src clock pair. 34 vddsrc pwr supply for src clocks, 3.3v nominal 35 cpuclkc2_itp/srcclkc7 out complimentary clock of cpu_itp/src differential pair cpu_itp/src output. these are current mode outputs. external resistors are required for voltage bias. selected by itp_en input. 36 cpuclkt2_itp/srcclkt7 out true clock of cpu_itp/src differential pair cpu_itp/src output. these are current mode outputs. external resistors are required for voltage bias. selected by itp_en input. 37 vdda pwr 3.3v power for the pll core. 38 gnda pwr ground pin for the pll core. 39 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 40 cpuclkc1 out complimentary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 42 vddcpu pwr supply for cpu clo cks, 3.3v nominal 43 cpuclkc0 out complimentary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 44 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 45 gnd pwr ground pin. 46 sclk in clock pin of smbus circuitry, 5v tolerant. 47 sdata i/o data pin for smbus circuitry, 5v tolerant. 48 vddref pwr ref, xtal pow er supply, nominal 3.3v 49 x2 out crystal output, nominally 14.318mhz 50 x1 in crystal input, nominally 14.318mhz. 51 gnd pwr ground pin. 52 refout out reference clock output 53 fs_c/test_sel in 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values. test_sel: 3-level latched input to enable test mode. refer to test clarification table 54 cpu_stop# in stops all cpuclk, except those set to be free running clocks 55 pci/src_stop# in stops all pciclks and srcclks besides the free-running clocks at logic 0 level, when i nput low 56 pciclk2 out pci clock output.
4 integrated circuit systems, inc. ics954201 0819h?02/17/06 ics954201 is a ck410m yellow cover clock synthesizer. ics954201 provides a single-chip solution for mobile systems built with intel p4-m processors and intel mobile chipsets. ics954201 is driven with a 14.318mhz crystal and generates cpu outputs up to 400mhz. it provides the tight ppm accuracy required by serial ata and pci-express. general description block diagram power groups vdd gnd 48 51 xtal, ref 1,7 2,6 pciclk outputs 21,28,34 29 srcclk outputs 37 38 master clock, cpu analog 11 13 dot, usb, pll_48 42 45 cpuclk clocks description pin number prog. spread main pll pciclk(5:2) control logic xtal osc. cpuclk(1:0) fixed pll usb_48mhz divider prog. dividers ref srcclk(6:0) itp_en sdata sclk test_mode x1 x2 iref fs(c:a) test_sel vtt_pwrgd#/pd dot_ 9 6mhz pciclk_f(1:0) cpuclk2_itp/srcclk7 pci/src_stop# cpu_stop#
5 integrated circuit systems, inc. ics954201 0819h?02/17/06 general i 2 c serial interface information for the ics954201 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
6 integrated circuit systems, inc. ics954201 0819h?02/17/06 absolute max symbol parameter min max units vdd_a 3.3v core supply voltage v dd + 0.5v v vdd_in 3.3v logic input supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v 1 low threshold input low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating supply current i dd3. 3op full active, c l = full load; 278 400 ma all diff pairs driven 67 70 ma all differential pairs tri-stated 4.8 12 ma input frequency 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from v dd power-up or de- assertion of pd# to 1st clock 1.3 1.8 ms 1,2 modulation frequency triangular modulation 30 33 khz 1 tdrive_src src output enable after pci_stop de-assertion 810ns1 tdrive_pd differential output enable after pd# de-assertion 300 us 1 tfall_pd pd# fall time of 5 ns 1 trise_pd pd# rise time of 5 ns 2 tdrive_cpu_stop cpu output enable after cpu_stop de-assertion 810ns1 tfall_cpu_stop cpu_stop fall time of 5 ns 1 trise_cpu_stop# cpu_stop rise time of 5 ns 2 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol sdata, sclk @ i pullup 0.4 v 1 current sinking i pullup v ol = 0.4 v 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1,3 sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1,3 1 guaranteed by design, not 100% tested in production. 2 see timing diagrams for timing requirements. 3 in p ut fre q uenc y should be measured at the ref out p ut p in and tuned to ideal 14.31818mhz to meet input low current powerdown current i dd3.3pd input capacitance 1
7 integrated circuit systems, inc. ics954201 0819h?02/17/06 electrical characteristics - src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 760 850 1,3 volta g e low vlow -150 2 150 1,3 max volta g e vovs 782 1150 1 min volta g e vuds -300 -33 1 crossing voltage (abs) vcross ( abs ) 250 344 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 97 140 mv 1 long accuracy ppm see t p eriod min-max values -300 300 ppm 1,2 100.00mhz non-spread 9.9999 10.0030 ns 2 100.00mhz s p read 10.0533 ns 2 100.00mhz non-spread 9.9999 10.1280 ns 1,2 100.00mhz spread 10.1783 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 260 700 ps 1 fall time t f v oh = 0.525v, v ol = 0.175v 175 212 700 ps 1 rise time variation d-t r 20 125 ps 1 fall time variation d-t f 13 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 51 55 % 1 skew t sk3 v t = 50% 87 250 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 37 125 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 9.8720 absolute min/max period t abs mv measurement on single ended signal using absolute value. mv average period t period statistical measurement on single ended signal using oscilloscope 9.9970
8 integrated circuit systems, inc. ics954201 0819h?02/17/06 electrical characteristics - cpu 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 voltage high vhigh 660 727 850 1,3 voltage low vlow -150 -2 150 1,3 max volta g e vovs 752 1150 1 min volta g e vuds -300 -21 1 crossing voltage (abs) vcross ( abs ) 250 348 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 39 140 mv 1 lon g accurac y pp m see t p eriod min-max values -300 300 pp m1,2 400mhz non-spread 2.4993 2.4999 2.5008 ns 2 400mhz s p read 2.4993 2.5133 ns 2 333.33mhz non-spread 2.9991 3.0000 3.0009 ns 2 333.33mhz s p read 2.9991 3.016 ns 2 266.66mhz non-spread 3.7489 3.7509 3.7511 ns 2 266.66mhz s p read 3.7489 3.77 ns 2 200mhz non-spread 4.9985 4.9998 5.0015 ns 2 200mhz s p read 4.9985 5.0266 ns 2 166.66mhz non-spread 5.9982 6.0000 6.0018 ns 2 166.66mhz s p read 5.9982 6.0320 ns 2 133.33mhz non-spread 7.4978 7.5017 7.5023 ns 2 133.33mhz s p read 7.4978 5.4000 ns 2 100.00mhz non-s p read 9.9970 10.0000 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 400mhz non-spread 2.4970 2.5750 ns 1,2 400mhz s p read 2.5983 ns 1,2 333.33mhz non-spread 2.9940 3.0859 ns 1,2 333.33mhz s p read 3.1010 ns 1,2 266.66mhz non-spread 3.7430 3.8361 ns 1,2 266.66mhz s p read 3.8550 ns 1,2 200mhz non-spread 4.9940 5.0865 ns 1,2 200mhz s p read 5.1116 ns 1,2 166.66mhz non-spread 5.9950 6.0868 ns 1,2 166.66mhz s p read 6.1170 ns 1,2 133.33mhz non-spread 7.4970 7.5873 ns 1,2 133.33mhz s p read 7.6250 ns 1,2 100.00mhz non-spread 10.0000 10.0880 ns 1,2 100.00mhz s p read 10.1383 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 230 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 206 700 ps 1 rise time variation d-t r 15 125 ps 1 fall time variation d-t f 14 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 51 55 % 1 cpu(1:0), v t = 50% 7.5 100 ps 1 cpu2_itp, v t = 50% 145 150 ps 1 jitter, cycle to cycle t jcyc-cyc differential waveform measurement, cpu ( 1:0 ) 36 85 ps 1 jitter, cycle to cycle t jcyc-cyc differential waveform measurement, cpu2_itp 96 125 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 2.4143 2.9141 average period t period absolute min/max period t abs 9.9120 statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv skew t sk3 3.6639 4.9135 5.9132 7.4128
9 integrated circuit systems, inc. ics954201 0819h?02/17/06 electrical characteristics - pciclk/pciclk_f t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 35 300 ppm 1,2 33.33mhz output non-spread 29.9989 30.0090 ns 2 33.33mhz output spread 30.0752 30.1598 ns 2 33.33mhz output non-spread 30.5090 ns 1,2 33.33mhz output spread 30.6598 ns 1,2 output hi g h volta g ev oh i oh = -1 ma 2.4 3.25 v 1 output low volta g ev ol i ol = 1 ma 0.05 0.55 v 1 v oh @min = 1.0 v -33 -62 ma 1 v oh @ max = 3.135 v -10 -33 ma 1 v ol @ min = 1.95 v 30 61 ma 1 v ol @ max = 0.4 v 23 38 ma 1 edge rate rising edge rate 1 1.60 4 v/ns 1 edge rate falling edge rate 1 1.71 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.25 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.17 2 ns 1 duty cycle d t1 v t = 1.5 v 45 50 55 % 1 skew t sk1 v t = 1.5 v 81 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 250 500 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 all lon g term accuracy and clock period specifications are g uaranteed assumin g that refout is at 14.31818mhz output low current i ol clock period t period output high current i oh 29.9910 absolute min/max period t abs 29.4910 electrical characteristics - 48mhz, usb t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accuracy ppm see tperiod min-max values -100 0.25 100 ppm 1,2 clock period t p eriod 48.00000 mhz output 20.8313 20.8333 20.8354 ns 2 absolute min/max period t abs 48.00000 mhz output 20.4813 21.1854 ns 1,2 output high voltage v oh i oh = -1 ma 2.4 3.25 v 1 output low voltage v ol i ol = 1 ma 0.05 0.55 v 1 v oh @ min = 1.0 v -29 -53 ma 1 v oh @ max = 3.135 v -6.2 -23 ma 1 v ol @min = 1.95 v 29 61 ma 1 v ol @ max = 0.4 v 23 27 ma 1 ed g e rate risin g ed g e rate 1 1.53 2 v/ns 1 edge rate falling edge rate 1 1.68 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.31 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.19 2 ns 1 duty cycle d t1 v t = 1.5 v 45 52 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 139 350 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 all lon g term accuracy and clock period specifications are g uaranteed assumin g that refout is at 14.31818mhz output low current i ol output high current i oh
10 integrated circuit systems, inc. ics954201 0819h?02/17/06 electrical characteristics - dot, 96mhz 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ?, ref = 475? parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 749 850 1,3 volta g e low vlow -150 1.5 150 1,3 max volta g e vovs 778 1150 1 min volta g e vuds -300 -51 1 crossing voltage (abs) vcross ( abs ) 250 358 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 26 140 mv 1 long accuracy ppm see t p eriod min-max values -100 100 ppm 1,2 average period t period 96.00mhz 10.4156 10.4167 10.4177 ns 2 absolute min/max period t abs 96.00mhz 10.1656 10.4100 10.6677 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 210 700 ps 1 fall time t f v oh = 0.525v, v ol = 0.175v 175 180 700 ps 1 rise time variation d-t r 23 125 ps 1 fall time variation d-t f 50 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 49 55 % 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 98 250 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is at 14.31818mhz 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . measurement on single ended signal using absolute value. mv statistical measurement on single ended signal using oscilloscope mv electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbo l conditions min typ max units notes lon g accuracy ppm see tperiod min-max values -300 300 ppm 1 clock period t p eriod 14.318mhz output nominal 69.8270 69.841 69.8550 ns 1 output high voltage v oh i oh = -1 ma 2.4 3.25 v 1 output low voltage v ol i ol = 1 ma 0.05 0.4 v 1 v oh @ min = 1.0 v -33 -53 ma 1 v oh @ max = 3.135 v -6 -33 ma 1 v ol @min = 1.95 v 30 60.9 ma 1 v ol @ max = 0.4 v 23 38 ma 1 v oh @ min = 1.0 v -33 -110 ma 1 v oh @ max = 3.135 v -12 -33 ma 1 v ol @min = 1.95 v 110 ma 1 v ol @ max = 0.4 v 47 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.7 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.9 2 ns 1,2 duty cycle d t1 v t = 1.5 v 45 54 55 % 1,2 jitter t jcyc-cyc v t = 1.5 v 197 1000 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 all lon g term accuracy and clock period specifications are g uaranteed assumin g that refout is at 14.31818mhz output high current (2x) i oh output low current (2x) i ol output high current (1x) i oh output low current (1x) i ol
11 integrated circuit systems, inc. ics954201 0819h?02/17/06 smbus table: output control register pin # nam e control function t yp e0 1 pwd bit 7 cpuclk2_itp/srcclk7 enable output enable rw disable enable 1 bit 6 srcclk6 enable output enable rw disable enable 1 bit 5 srcclk5 enable output enable rw disable enable 1 bit 4 srcclk4 enable output enable rw disable enable 1 bit 3 srcclk3 enable output enable rw disable enable 1 bit 2 srcclk2 enable output enable rw disable enable 1 bit 1 srcclk1 enable out p ut enable rw disable enable 1 bit 0 srcclk0 enable output enable rw disable enable 1 smbus table: spreading and device behavior control register pin # nam e control function t yp e0 1 pwd bit 7 pci_f0 enable output enable rw disable enable 1 bit 6 dot_96mhz enable output enable rw disable enable 1 bit 5 usb_48mhz enable output enable rw disable enable 1 bit 4 refout enable output enable rw disable enable 1 bit 3 1 bit 2 cpuclk1 output enable rw disable enable 1 bit 1 cpuclk0 output enable rw disable enable 1 bit 0 spread spectrum mode spread off rw spread off spread on 0 smbus table: output control register pin # nam e control function t yp e0 1 pwd bit 7 pciclk5 output enable rw disable enable 1 bit 6 pciclk4 output enable rw disable enable 1 bit 5 pciclk3 out p ut enable rw disable enable 1 bit 4 pciclk2 out p ut enable rw disable enable 1 bit 3 1 bit 2 1 bit 1 1 bit 0 pci_f1 enable output enable rw disable enable 1 reserved reserved reserved b y te 2 b y te 0 - - - - - - - reserved - b y te 1
12 integrated circuit systems, inc. ics954201 0819h?02/17/06 smbus table: src stop control register pin # name control function t yp e0 1 pw d bit 7 srcclk7 rw free-runnin g sto pp abl e 0 bit 6 srcclk6 rw free-running stoppable 0 bit 5 srcclk5 rw free-running stoppable 0 bit 4 srcclk4 rw free-running stoppable 0 bit 3 srcclk3 rw free-running stoppable 0 bit 2 srcclk2 rw free-running stoppable 0 bit 1 srcclk1 rw free-runnin g sto pp abl e 0 bit 0 srcclk0 rw free-running stoppable 0 smbus table: stop and output control register pin # name control function t yp e0 1 pw d bit 7 x bit 6 dot_96mhz driven in pd rw driven hi-z 0 bit 5 0 bit 4 pci_f1 rw free-running stoppable 0 bit 3 pci_f0 rw free-running stoppable 0 bit 2 cpuclk2_itp rw free-runnin g sto pp abl e 1 bit 1 cpuclk1 rw free-runnin g sto pp abl e 1 bit 0 cpuclk0 rw free-running stoppable 1 smbus table: output control register pin # name control function t yp e0 1 pw d bit 7 src_stop drive mode driven in pci/src_stop# rw driven hi-z 0 bit 6 cpuclk2_itp_stop drive mode rw driven hi-z 0 bit 5 cpuclk1_stop drive mode rw driven hi-z 0 bit 4 cpuclk0_stop drive mode rw driven hi-z 0 bit 3 src_pd drive mode rw driven hi-z 0 bit 2 cpuclk2_itp_pd drive mode rw driven hi-z 0 bit 1 cpuclk1_pd drive mode rw driven hi-z 0 bit 0 cpuclk0_pddrive mode rw driven hi-z 0 driven in cpu_stop# driven in powerdown (pd) allow assertion of pci_stop# or setting of pci_stop control bit in smbus register to stop pciclk_f outputs reserved allow assertion of cpu_stop# to stop cpuclk outputs reserved allow assertion of pci_stop# or setting of pci_stop control bit in smbus register to stop src clocks 41,40 44,43 44,43 srcclk(7:0) 36,35 44,43 9 31,30 26,27 8 36,35 41,40 24,25 22,23 19,20 b y te 4 17,18 b y te 3 36,35 33,32 b y te 5 srcclk(7:0) 36,35 41,40 14,15
13 integrated circuit systems, inc. ics954201 0819h?02/17/06 smbus table: test and readback control register pin # name control function t yp e0 1 pwd bit 7 test mode selection test mode selection rw hi-z ref/n 0 bit 6 test clock mod eentr y test mode rw disable enable 0 bit 5 0 bit 4 refout strength strength prog rw 1x 2x 1 bit 3 pci/src_stop stop all pci and src clocks rw enabled disabled 1 bit 2 fs_c readback r - - latched bit 1 fs_b readback r - - latched bit 0 fs_a readback r - - latched smbus table: vendor & revision id register pin # name control function t yp e0 1 pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 reserved - vendor id - - - b y te 7 - revision id - - - - - - - - - - - b y te 6 test clarification table comments fs_c/test _sel hw pin fs_b/test _mode hw pin test entry bit b6b6 ref/n or hi-z b6b7 output 0x0xnormal 10x0hi-z 10x1ref/n 11x0ref/n 11x1ref/n 0x10hi-z 0x11ref/n b6b6: 1= enter test mode, default = 0 (normal operation) b6b7: 1= ref/n, default = 0 (hi-z) hw sw fs_c/test_sel is a 3-level latched input. o power-up w/ v >= 2.0v to select test o power-up w/ v < 2.0v to have pin function as fs_c. when pin is fs_c, vih_fs and vil_fs levels apply. fs_b/test_mode is a low-threshold input o vih_fs and vil_fs levels apply. o test_mode is a real time input test_sel can be invoked after power up through smbus b6b6. o if test is selected by b6b6, only b6b7 controls test_mode. the fs_b/test_mode pin is not used. power must be cycled to exit test.
14 integrated circuit systems, inc. ics954201 0819h?02/17/06 min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a0808 variations min max min max 56 18.31 18.55 .720 .730 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d (inch) symbol see variations see variations index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l ordering information ics954201 y flxt example: designation for tape and reel packaging ln or lf = lead free, rohs compliant package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) prefix ics, av = standard device ics xxxx y f lx t
15 integrated circuit systems, inc. ics954201 0819h?02/17/06 in d ex a r ea in d ex a r ea 1 2 1 2 n d e1 e s eatin g p lane s eatin g p lane a1 a a 2 a 2 e - c - - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10-0039 56-lead 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, m o-153 ordering information ics954201 y glxt example: designation for tape and reel packaging ln or lf = lead free, rohs compliant package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) prefix ics, av = standard device ics xxxx y g lxt
16 integrated circuit systems, inc. ics954201 0819h?02/17/06 revision history rev. issue date description page # h 2/17/2006 updated lead free orderin g information. 14-15

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